The invention relates to a test method for determining the wire configuration for a circuit carrier having at least one component arranged thereon, with connections of the component being wired to connections of the circuit carrier. The invention also relates to a memory module test system for carrying out the method on memory modules having memory chips arranged thereon.
Electronic components or integrated circuits, such as memory chips, are normally accommodated on circuit carriers, such as circuit boards or modules, which can then be used flexibly, for example in PCs, and have standardized connections.
In particular, memory modules having memory chips are known. Before memory modules are delivered, however, the functionality of the components or memory chips used needs to be checked by tests during production. Such memory tests involve address and data sequences being written and read by a memory tester, which allows errors to be identified within the chips. By way of example, electrical coupling between data or word lines is identified by writing appropriate data patterns and subsequently reading them using the memory tester.
FIG. 1 shows an example of a memory chip 1 which has a memory cell array 2 with word and bit lines 3, 4. The bit lines or data lines 4 are driven by cell array amplifiers 5. By way of example, FIG. 1 shows four bit lines 4-1, 4-2, 4-3, 4-4, which are routed to connections 6-1, 6-2, 6-3, 6-4 of the memory chip.
These bit lines or data lines are used for inputting and outputting data. The read/write access operations to such a memory chip are controlled by further control signals, which are input at further connections 7, 8, 9 of the memory chip 1. During the manufacture of the memory chips 1, the association between the data lines 4 and the data connections of the memory chips 6-1, 6-2, 6-3, 6-4 is known. This is necessary in order to write particular test patterns to the memory cell array.
FIG. 2 shows an example of a memory module 10 with four memory chips 11, 12, 13, 14 which each have data connections 15, 16, 17, 18 which are wired to data connections 19, 20, 21, 22 of the memory module 10. Often the exact wire configuration is unknown, which is shown by the blocks 23, 24, 25, which are caused by unknown transposition or unknown scrambling of the wire configuration. In order to write particular test patterns to the appropriate memory cell arrays in order to test the memory chips 11, 12, 13, 14 which are used on the memory module 10, however, exact knowledge of the wire configuration between the data connections of the memory chips 11, 12, 13, 14 and the data connections 19, 20, 21, 22 of the module 10 is required. If the documentation about this wire configuration is incorrect or entirely unknown, for example, then it is not possible to actuate adjacent data or bit lines specifically, which is necessary for tests which check coupling between memory cells.
For operation of the memory module, it is not necessary to have exact knowledge of the position of the data lines in the respective memory chips 11, 12, 13, 14, since the position of the memory cells is of no significance for storing and reading. In order to test the functionality of the memory module 10 and hence also to check coupling, for example, between data lines in the memory chips 11, 12, 13, 14 which are used, however, the internal data lines of the memory chips 11, 12, 13, 14 need to be a able to be actuated specifically, i.e. the wire configuration between the memory chip connections 15, 16, 17, 18 and the module connections 19, 20, 21, 22 needs to be known. This is because only then is it possible to apply appropriate test patterns for the memory cell arrays.